Venky

A LoRA adapter for Qwen2.5-Coder-7B-Instruct that predicts, from the code alone, whether a Verilog design change will fail its test bench before any simulator is run. It exists to sit in front of the expensive evaluation stage of an agentic hardware design loop. Simulation is slow and costly, and many agent proposals are simply wrong. This model triages them. Every frontier model tested carries the same wrong prior: that any edit to working code is probably a bug. That produces near-perfect recall and poor precision, so the gate throws away a large share of perfectly good designs. This adapter was trained on data containing verified-harmless edits alongside real faults, which attacks that…