A collection of 284,177 public GitHub repositories written in Verilog, SystemVerilog or VHDL, filtered down to the files relevant to hardware design and verification: RTL source, testbenches (UVM, plain SV/V/VHDL, cocotb, VUnit), golden/reference models, vendor IP configuration, the data files those sources read at simulation time, and each project's own documentation and build scripts. It was built for two purposes: a test corpus for Lumees Lab's HDL lint tool, and a source corpus for internal model research. It is not licensed for AI training by anyone who requests access — see Licensing and usage below. Lint tools and language-model training both need large, realistic bodies of…