Animagine XL 3.1 with the SDXL-Lightning 4-step LoRA fused in, its UNet quantised to w8a16 (int8 weights, int16 activations) with Qualcomm AI Hub and compiled to a Hexagon NPU context binary for the Snapdragon 8 Gen 3 (QAIRT 2.45). 1024x1024 in 4 steps, about 11 seconds on a Snapdragon 8 Gen 3 including load. Full-size SDXL does not fit one HTP graph in fp16 (~5.5 GB against a 3.5 GB limit); int8 weights bring the UNet to 2.6 GB. The graph has fp32 IO bound by timeids -> output0. Context binaries are per chip generation. The VAE decoder comes from latentdivergence/lcm-ssd1b-npu-, the text encoders from latentdivergence/animagine-xl-lightning-int8, the tokenizer from…
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latentdivergence
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Models on Hugging Face41
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